The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming an isolation layer, which is able to prevent generation of a moat, and a method for fabricating a nonvolatile memory device using the same.
Recently, researches for a so-called charge trap device (CTD) such as a charge trap type nonvolatile memory device are actively in progress to implement a large-scaled nonvolatile memory device of sub-40 nm dimensions. The charge trap type nonvolatile memory device has a stacked structure where a tunnel insulation layer, a charge trap layer, a dielectric layer and a gate electrode are sequentially stacked over a substrate and stores data by trapping or capturing charge in a trap site within the charge trap layer, wherein the trap site has a significant depth.
Meanwhile, since the charge trap type nonvolatile memory device is constructed of the combination of a plurality of unit memory devices, it requires an isolation layer to electrically isolate the unit memory devices from each other. In general, the isolation layer is formed by a shallow trench isolation (STI) method employing a trench structure.
FIGS. 1A to 1C illustrate a method for fabricating a charge trap type nonvolatile memory device in the prior art.
Referring to FIG. 1A, a tunnel insulation layer 12, a charge trap layer 13, a buffer oxide layer 14 and a hard mask nitride pattern 15 are sequentially formed over a substrate 11.
Then, after forming a trench 16 for the device isolation by etching the buffer oxide layer 14, the charge trap layer 13, the tunnel insulation layer 12 and the substrate 11 using the hard mask nitride pattern 15 as an etch barrier, an isolation layer 17 is formed by filling the trench 16 with an insulation material. Herein, the isolation layer 17 is formed using an oxide layer having a relatively superior filling characteristic, e.g., a spin on dielectric (SOD) layer, to prevent the generation of defects such as seams within the layer.
Referring to FIG. 1B, a wet etch process is performed to remove the hard mask nitride pattern 15. The hard mask nitride pattern 15 is removed using a phosphoric acid solution.
Subsequently, a cleaning process is performed to remove residue and the buffer oxide layer 14, thereby exposing the top surface of the charge trap layer 13. The cleaning process is performed using a hydro fluoric acid solution.
Referring to FIG. 1C, after forming a dielectric layer 18 along the entire surface of a resultant structure including the isolation layer 17, a gate electrode 19 is formed on the dielectric layer 18.
However, in the prior art, as the edge of the isolation layer 17 may be damaged during the process of removing the hard mask nitride pattern 15, moat (M) is generated. This is because the SOD layer used as the isolation layer 17 may contain impurities such as carbon and a lot of minute defects such as voids formed therein and thus may be comparatively easily etched by the phosphoric acid solution. Furthermore, the moat (M) becomes more serious concern in the cleaning process since the isolation layer 17 and the buffer oxide layer 14 are formed of the same oxide layer and thus the isolation layer 17 is also etched by the hydro fluoric acid solution used in the cleaning process.
Moreover, it is preferable to form the dielectric layer 18 having uniform thickness over the resultant structure so that the unit memory devices of the nonvolatile memory device have uniform performance characteristics. However, since the moat (M) has a horn shape and the dielectric layer 18 has relatively small thickness around the moat (M), it is difficult to form the dielectric layer 18 having the uniform thickness over the resultant structure, as shown in a portion indicated by a reference numeral B in FIG. 1C.
In addition, it is preferable that the charge trap layer 13 and the gate electrode 19 are electrically separated from each other by the dielectric layer 18 to enable a normal operation of the nonvolatile memory device. However, there is a concern that a coupling ratio of the charge trap layer 13 and the gate electrode 19 is changed by an electrical short through an opening in the dielectric layer 18 in the area of the moat (M), as shown in a portion indicated by a reference numeral A in FIG. 1C.